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Mixed-Signal IC

Modern embedded mixed-signal platforms are increasingly relying on “scalable circuits,” which are portable across technology nodes and programmable to a certain extent. However, analog design shows some resilience to sharing, flexibility, and design reuse. The design of analog and mixed-signal (AMS) and RF circuits, which are indispensable system-on-chip components, is still an “art” and does not extensively use abstractions and decompositions within a structured methodology.

My research in the AMS design area has focused on innovative, scalable architectures for energy-efficient analog-to-digital converters (ADC) and low-noise frequency synthesizers for wireless communication.

Energy-Efficient Analog and Mixed-Signal Circuit Design

Selected Publications

  • P. Nuzzo, C. Nani, C. Armiento, A. Sangiovanni-Vincentelli, J. Craninckx and G. Van der Plas, “A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS,” IEEE Transactions on Circuits and Systems-I: Regular papers, vol. 58, n. 12, Dec. 2011.
  • V. Giannini, P. Nuzzo, C. Soens,  K. Vengattaramane, J. Ryckaert, M. Goffioul, B. Debaillie, J. Borremans, J. Van Driessche, J. Craninckx, M. Ingels, “A 2-mm^2 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS,” IEEE Journal of Solid State Circuits, vol. 44, no.12, Dec. 2009, pp. 3486-3498.
  • A. Geis, P. Nuzzo, J. Ryckaert, Y. Rolain, G. Vandersteen, J. Craninckx, “An 11.6-19.3mW 0.375-13.6GHz CMOS Frequency Synthesizer With Rail-to-Rail Operation,” Proc. Design Automation and Testing in Europe Conference (DATE), 2010.
  • P. Nuzzo, C. Nani, C. Armiento, A. Sangiovanni-Vincentelli, J. Craninckx, G. Van der Plas, “A 6-bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS,” Proc. VLSI Symposium on Circuits, Kyoto, Japan, June 2009, pp. 238-239.
  • P. Nuzzo, K. Vengattaramane, M. Ingels, V. Giannini, M. Steyaert, J. Craninckx, “A 0.1-5GHz, Dual-VCO Software-Defined Sigma-Delta Frequency Synthesizer in 45nm Digital CMOS,” Proc. RFIC Symposium, Boston, MA, June 2009, pp. 321-324.
  • V. Giannini, P. Nuzzo, C. Soens, K. Vengattaramane, M. Steyaert, J. Ryckaert, M. Goffioul, B. Debaillie, J. Van Driessche, J. Craninckx, M. Ingels, “A 2mm^2 0.1-5GHz SDR Receiver in 45nm Digital CMOS,” Int. Solid State Circuit Conf. Dig. Tech. Papers, p. 408, Feb. 2009.