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Similar design concepts can be applied, from large-scale cyber-physical systems (CPSs) down to systems-on-chip (SoCs), to address similar design challenges in terms of complexity and heterogeneity. SoCs integrate both analog and digital subsystems on the same substrate. While digital design has benefited from electronic design automation (EDA), analog and mixed-signal (AMS) circuits heavily rely on manual design and integration efforts and remain one of the main bottlenecks of current design flows. Moreover, while integrated circuits (ICs) are often expected to provide the “root of trust” of today’s cyber-physical and Internet-of-Things (IoT) systems, the globalization of the IC and associated supply chains may pose serious threats to these systems, which are critical to national security, infrastructure, and economy. Supported by the Defense Advanced Research Projects Agency (DARPA), our research draws from our expertise in AMS design and its automation to tackle important challenges in secure and trustworthy SoC design. |
MIRAGE: Security-Driven IC Obfuscation Design
Modern systems-on-chip (SoCs) combine multiple processor cores and specialized Intellectual Property (IP) blocks that are designed and integrated by different companies, each of them with specific expertise (e.g., video processing, machine learning). This raises the risk of security threats from untrusted third parties. In fact, integrated circuit (IC) design companies increasingly outsource also the physical fabrication of their devices to third party foundries to save on fabrication costs. Overall, the globalization of the IC and associated supply chains poses serious threats to national security, infrastructure, and economy.
Hardware “obfuscation” methods have been proposed over the years to protect the designs from threats such as IP piracy, reverse engineering, and hardware Trojan insertion. However, there has been little agreement on metrics, much less on end-user tools to select and assess obfuscation methods and apply them to the most sensitive parts of a circuit. The MIRAGE project aims to develop a system-level end-to-end framework for integrated circuit obfuscation that addresses these challenges, effectively raising the level of abstraction at which we can reason and make informed decisions about IC protection.
Relevant Papers:
- Hu, V. V. Menon, A. Schmidt, J. Monson, M. French, and P. Nuzzo, “Security-driven Metrics and Models for Efficient Evaluation of Logic Encryption Schemes,” Proc. IEEE/ACM Int. Conf. on Formal Methods and Models for System Design (MEMOCODE), p. 9, pp. 1-5, Oct. 2019.
- V. Menon, G. Kolhe, A. Schmidt, J. Monson, M. French, Y. Hu, P. A. Beerel, P. Nuzzo, “System-Level Framework for Logic Obfuscation with Quantified Metrics for Evaluation,” IEEE Cybersecurity Development Conf. (SecDev), pp. 89-100, Sep. 2019.
Energy-Efficient Analog and Mixed-Signal Circuit Design
Modern embedded mixed-signal platforms are increasingly relying on “scalable circuits,” which are portable across technology nodes and programmable to a certain extent. However, analog design shows some resilience to sharing, flexibility, and design reuse. The design of analog and mixed-signal (AMS) and RF circuits, which are indispensable system-on-chip components, is still an “art” and does not extensively use abstractions and decompositions within a structured methodology. Our research in the AMS design area has focused on innovative, scalable architectures for energy-efficient analog-to-digital converters (ADC) and low-noise frequency synthesizers for wireless communication. We have also contributed platform-based and contract-based mixed-signal design methodologies that can raise the level of abstraction of analog design and enable hierarchical and compositional design of complex SoCs, including novel approaches for modeling the performance of analog components based on design constraint graphs, principled generation of simulation data, and statistical learning to enable automatic system-level design space exploration.
Selected Publications:
- P. Nuzzo, C. Nani, C. Armiento, A. Sangiovanni-Vincentelli, J. Craninckx and G. Van der Plas, “A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS,” IEEE Transactions on Circuits and Systems-I: Regular papers, vol. 58, n. 12, Dec. 2011.
- V. Giannini, P. Nuzzo, C. Soens, K. Vengattaramane, J. Ryckaert, M. Goffioul, B. Debaillie, J. Borremans, J. Van Driessche, J. Craninckx, M. Ingels, “A 2-mm^2 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS,” IEEE Journal of Solid State Circuits, vol. 44, no.12, Dec. 2009, pp. 3486-3498.
- A. Geis, P. Nuzzo, J. Ryckaert, Y. Rolain, G. Vandersteen, J. Craninckx, “An 11.6-19.3mW 0.375-13.6GHz CMOS Frequency Synthesizer With Rail-to-Rail Operation,” Proc. Design Automation and Testing in Europe Conference (DATE), 2010.
- P. Nuzzo, C. Nani, C. Armiento, A. Sangiovanni-Vincentelli, J. Craninckx, G. Van der Plas, “A 6-bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS,” Proc. VLSI Symposium on Circuits, Kyoto, Japan, June 2009, pp. 238-239.
- P. Nuzzo, K. Vengattaramane, M. Ingels, V. Giannini, M. Steyaert, J. Craninckx, “A 0.1-5GHz, Dual-VCO Software-Defined Sigma-Delta Frequency Synthesizer in 45nm Digital CMOS,” Proc. RFIC Symposium, Boston, MA, June 2009, pp. 321-324.
- V. Giannini, P. Nuzzo, C. Soens, K. Vengattaramane, M. Steyaert, J. Ryckaert, M. Goffioul, B. Debaillie, J. Van Driessche, J. Craninckx, M. Ingels, “A 2mm^2 0.1-5GHz SDR Receiver in 45nm Digital CMOS,” Int. Solid State Circuit Conf. Dig. Tech. Papers, p. 408, Feb. 2009.
- P. Nuzzo, F. De Bernardinis, P. Terreni, G. Van der Plas, “Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures,” IEEE Transactions on Circuits and Systems-I: Regular papers, vol. 55, no. 6, pp. 1441-1454, Jul. 2008.